As computer architecture, the von Neumann architecture is generally known in which instructions are sequentially fetched from a storage device (memory), decoded, and executed. This von Neumann architecture is a processing system with emphasis on instructions, in which an execution sequence of the instructions is determined in advance and processing is performed while operands (data to be calculated) are collected each time.
Further, in von Neumann computers, as CPU (Central Processing Unit) architecture that performs parallel processing of a plurality of instructions, superscalar processers are known. The superscalar processor is capable of out-of-order processing in which an instruction is issued to an execution node in the order of arrival of the operands, to be executed. However, in the superscalar processors, since a scheduler rearranges execution results in a right order while inspecting data dependency, an increase in the number of instructions that can be executed at the same time causes complication of the scheduler.
On the other hand, as non-von Neumann architecture, data-driven architecture is known, in which the data dependency is focused and processing is performed in accordance with a data flow (flow of data). This data-driven architecture is capable of processing many instructions in parallel by firing at the point of the time when the operands are ready in the execution node and by transferring the execution result of the instruction to the subsequent execution node.
For example, in Patent Document 1, a multi-processor system is disclosed in which the data-driven (data flow machine type in Patent Document 1) architecture is used for control between processors and the Neumann architecture is used for control in the processor, respectively. This multi-processor system is capable of performing parallel processing on the basis of the executable code generated by being divided into threads using the data-driven architecture and the Neumann architecture in combination without using a complicated hardware configuration.
Furthermore, for example, in Non-patent Document 1, TRIPS (Tera-op Reliable Intelligently Advanced Processing System) architecture is disclosed. This TRIPS architecture is a combination of chip architecture called tile processor and ISA (Instruction Set Architecture) called EDGE (Explicit Data Graph Execution). Among them, the tile processor is capable of keeping an operation speed high even if the number of cores is increased, by wiring only between the adjacent cores, so as to avoid a problem of wiring delay. On the other hand, the EDGE architecture aims at maximizing parallelism of processing by statically arranging the instructions in the execution node and executing them at the point of the time when the operands are ready in the execution node, similarly to the data flow architecture.
As such, a plurality of instructions can be processed in parallel by using the computer architectures as described above singly or in combination.